1. Field of the Invention
The present invention relates to a semiconductor apparatus, and particularly to a semiconductor apparatus capable of setting a test mode to an internal circuit from outside and a test execution method therefor.
2. Description of Related Art
A semiconductor apparatus has a test mode in order to test an internal circuit. In recent years, along with the increasing functions and higher integration of a semiconductor apparatus, kind of the test mode is also increasing. In the test mode, a mode setting signal is input for setting to the test mode from outside the semiconductor apparatus. Selection of the test mode is carried out according to the mode setting signal. The mode setting signal is usually a multibit digital signal.
Japanese Unexamined Patent Application Publication No. 2000-304831 discloses a semiconductor apparatus that is set to the test mode. The semiconductor apparatus disclosed in Japanese Unexamined Patent Application Publication No. 2000-304831 is shown in FIG. 6. A reset signal is input to the semiconductor apparatus from a reset terminal 67, and a clock signal is input to the semiconductor apparatus from a clock terminal 66. A control circuit 62 and shift register 63 are reset by the reset signal. In the test mode, a selector 61 connects an I/O terminal 65 with the shift register 63. Then a test mode control signal is input from the I/O terminal 65. A test mode control signal is latched by the shift register 63. The latched test mode control signal is decoded to a mode setting signal by a decoder 64. In the semiconductor apparatus, clocks corresponding to the time required to reset and clocks corresponding to the time required to set to test mode are determined in advance. The semiconductor apparatus switches the selector 61 when clocks input to the control circuit 62 reaches to the predetermined number of clocks. By doing this, the I/O terminal 65 is connected to the internal circuit.
As the semiconductor apparatus of FIG. 6 uses test terminals and I/O terminals corresponding to bits of the test mode setting signal, increasing test modes to set causes to increase external terminals. Further, as a signal for setting to test mode is input from the I/O terminal, the selector is connected to the I/O terminal. Since the selector is connected to the I/O terminal, an AC characteristic of an input/output signal at a normal operation mode may be deteriorated or delayed. As described in the foregoing, it has now been discovered that in the semiconductor apparatus, the number of terminals for setting to the test mode may increase. Further an influence may be generated to an input/output terminal at a normal time.